Asymmetrical Multilevel Inverter Topology with Reduced Number of Switches

被引：0
|
作者：
Ahmed, Rokan Ali [1 ]
Mekhilef, Saad [1 ]
Ping, Hew Wooi [1 ]
机构：
[1] Univ Malaya, Dept Elect Engn, Kuala Lumpur 50603, Malaysia
来源：
INTERNATIONAL REVIEW OF ELECTRICAL ENGINEERING-IREE | 2012年 / 7卷 / 04期
关键词：
Symmetrical Multilevel Inverter; Peak Inverse Voltage (PIV); Total Harmonic Distortion (THD); Voltage Drop; SYNCHRONOUS SERIES COMPENSATOR; MINIMUM NUMBER; VECTOR CONTROL; VOLTAGE; PWM; IMPLEMENTATION; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new asymmetrical multilevel inverter topology with reduced number of power switches is introduced in this paper. The installation area, voltage standing on each switch, converter cost and losses are also taken into consideration in this design. Further, operating principles and switching functions are analyzed. A comparative study between the new design and conventional inverters is also conducted to highlight the advantages of the proposed topology. Simulation results are provided for seven level of the asymmetrical multilevel inverter. A prototype of the designed inverter is manufactured and experimental results are realized. Copyright (C) 2012 Praise Worthy Prize S.r.l. - All rights reserved.
引用
收藏
页码：4761 / 4767
页数：7
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