Asymmetrical Multilevel Inverter Topology with Reduced Number of Switches

被引：0
|
作者：
Ahmed, Rokan Ali [1 ]
Mekhilef, Saad [1 ]
Ping, Hew Wooi [1 ]
机构：
[1] Univ Malaya, Dept Elect Engn, Kuala Lumpur 50603, Malaysia
来源：
INTERNATIONAL REVIEW OF ELECTRICAL ENGINEERING-IREE | 2012年 / 7卷 / 04期
关键词：
Symmetrical Multilevel Inverter; Peak Inverse Voltage (PIV); Total Harmonic Distortion (THD); Voltage Drop; SYNCHRONOUS SERIES COMPENSATOR; MINIMUM NUMBER; VECTOR CONTROL; VOLTAGE; PWM; IMPLEMENTATION; DESIGN;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new asymmetrical multilevel inverter topology with reduced number of power switches is introduced in this paper. The installation area, voltage standing on each switch, converter cost and losses are also taken into consideration in this design. Further, operating principles and switching functions are analyzed. A comparative study between the new design and conventional inverters is also conducted to highlight the advantages of the proposed topology. Simulation results are provided for seven level of the asymmetrical multilevel inverter. A prototype of the designed inverter is manufactured and experimental results are realized. Copyright (C) 2012 Praise Worthy Prize S.r.l. - All rights reserved.
引用
收藏
页码：4761 / 4767
页数：7
相关论文
共 50 条
  • [31] Performance Analysis of a Multilevel Inverter Topology with Reduced Switches
    Sravani, E.
    Reddy, N. Ravi Sankar
    [J]. 2015 INTERNATIONAL CONFERENCE ON COMPUTER, COMMUNICATION AND CONTROL (IC4), 2015,
  • [32] A New General Topology for Asymmetrical Multilevel Inverter with Reduced Number o Switching Components
    Boora, Kamaldeep
    Kumar, Jagdish
    Himanshu
    [J]. 2017 RECENT DEVELOPMENTS IN CONTROL, AUTOMATION AND POWER ENGINEERING (RDCAPE), 2017, : 66 - 71
  • [33] Symmetrical and Asymmetrical Multilevel Inverter using Less Number of switches
    Thakre, Kishor
    Mohanty, Kanungo Barada
    Kommukuri, Vinayasagar
    Mishra, Rabi Narayan
    [J]. TENCON 2017 - 2017 IEEE REGION 10 CONFERENCE, 2017, : 1032 - 1036
  • [34] New Grid-tied Cascaded Multilevel Inverter Topology with Reduced Number of Switches
    Sajedi, Shahab
    Basu, Malabika
    Farrell, Michael
    [J]. 2017 52ND INTERNATIONAL UNIVERSITIES POWER ENGINEERING CONFERENCE (UPEC), 2017,
  • [35] A Level Dependent Source Concoction Multilevel Inverter Topology with a Reduced Number of Power Switches
    Jose, S. Edwin
    Titus, S.
    [J]. JOURNAL OF POWER ELECTRONICS, 2016, 16 (04) : 1316 - 1323
  • [36] Simulation of New Symmetric and. Asymmetric Multilevel Inverter Topology with Reduced Number of Switches
    Thiyagarajan, V.
    Somasundaram, P.
    [J]. 2018 4TH INTERNATIONAL CONFERENCE ON ELECTRICAL ENERGY SYSTEMS (ICEES), 2018, : 315 - 319
  • [37] New Multilevel Inverter Topology with reduced number of Switches using Advanced Modulation Strategies
    Rao, S. Nagaraja
    Kumar, D. V. Ashok
    Babu, Ch Sai
    [J]. 2013 INTERNATIONAL CONFERENCE ON POWER, ENERGY AND CONTROL (ICPEC), 2013, : 693 - 699
  • [38] Novel Multilevel Inverter with Reduced Number of Switches and Batteries
    Deepak, Rashmy
    Kasturi, Vishnu S.
    Sarkar, Lepakshi
    Manjunatha, Y. R.
    Lakshmikantha, B. R.
    [J]. 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, CONTROLS AND COMMUNICATIONS (CCUBE), 2013,
  • [39] Asymmetric Multilevel Hybrid Inverter with Reduced Number of Switches
    Abraham, Babitha T.
    Benny, Anish
    [J]. 2014 ANNUAL INTERNATIONAL CONFERENCE ON EMERGING RESEARCH AREAS: MAGNETICS, MACHINES AND DRIVES (AICERA/ICMMD), 2014,
  • [40] A higher levels multilevel inverter with reduced number of switches
    Harbi, I. A.
    Azazi, Haitham Z.
    Lashine, Azza E.
    Elsabbe, Awad E.
    [J]. INTERNATIONAL JOURNAL OF ELECTRONICS, 2018, 105 (08) : 1286 - 1299
12345