An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires

An area efficient low-voltage 6-T SRAM cell using stacked silicon nanowires is proposed. Among emerging CMOS devices, nanowire (NW) / gate-all-around (GAA) silicon MOSFETs have shown advantages for scaling features as the semiconductor technology continues to progress. While preserving the intrinsic GAA advantages, this paper provides a design methodology for the optimal and feasible manufacturability with different doping concentrations to achieve high density design and assesses the performance via three-dimensional TCAD simulation. However, due to limited atoms in the extremely scaled channel, a heavy doping with in-situ doping process is needed. In addition, using vertical stacked gate-all-around MOSFETs to achieve high density in the same layout area with the proposed multi-threshold doping scheme is beneficial for system on chip (SoC) application. Circuit performance projection of the 6-T SRAM is provided based on balanced read and write performances.