Combinational divider in FPGA

被引：0
|
作者：
Kolouch, Jaromir [1 ]
机构：
[1] Brno Univ Technol, Dept Radio Elect, Brno 61200, Czech Republic
来源：
2007 17TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA, VOLS 1 AND 2 | 2007年
关键词：
arithmetic functions; combinational logic; integer division; synthesis; FPGA; propagation delay;
D O I：
暂无
中图分类号：
TN [电子技术、通信技术];
学科分类号：
0809 ;
摘要：
The possibility of synthesis of combinational divider for unsigned integer numbers in FPGA devices is considered with respect to recent technology development. Three VHDL models are discussed, and corresponding synthesis and implementation results - resource consumption and propagation delay, together with the bit width limitation, are compared.
引用
收藏
页码：47 / 50
页数：4
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