Thermal Modeling and Simulation of a Package-on-Package Embedded Micro Wafer Level Package (EMWLP) Structure at the Package and System-level

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this study's parametric thermal modeling focuses on analyzing the thermal impact of increased density in a low thermal conductivity packaging material. The package design in this work has the following specifications: the memory EMWLP (die size: 7x7x0.2mm) on logic EMWLP structure (die size : 8x8x0.2mm), sized 12x12x0.9mm in total. The POP structure, furthermore, incorporates through-mold-interconnects (TMI) in the bottom logic package to provide short electrical connection from the top package to the board level. The impact on multi-package thermal resistance is then studied as the following parameters vary: power dissipation (in both packages); mold conductivity; number of TMIs; number of solder ball connections; inclusion and size of an interpackage heatslug; inclusion and thermal conductivity of a top heatspreader. The thermal management of the dies are also studied based on the above measures and was found to accommodate under 4W of total POP power. Finally, simulation results for a general system-level thermal modeling of the EMWLP POP in a cellphone scenario are also conducted with passive thermal management solutions proposed.