Double Side Redistribution Layer Process on Embedded Wafer Level Package for Package on Package (PoP) Applications

In this paper, an embedded wafer level package with Cu through mold via (TMV) interconnects was developed for package on package (PoP) application. Cu pillar interconnects for different heights were fabricated on daisy chain test chips and sacrificial chips. The daisy chain test chips were then stacked onto the sacrificial chips using die attach film, and the chip stacks were picked and placed onto a molding tape for mold encapsulation to form a re-configured wafer. The re-configured wafer was mechanically backgrinded on both sides to remove sacrificial chips and to expose the Cu TMV. The thinned re-configured wafer was temporarily bonded to a stiff Si carrier using a temporary adhesive, in order to reduce the wafer warpage to enable wafer level processing of the Cu redistribution layers (RDL). After front side RDL processing, the re-configured wafer is de-bonded and re-bonded for backside RDL processing. The warpage value of the re-configured wafer was measured during different process steps and through-scan was performed using a scanning acoustic microscope to inspect the quality of temporary bonding of re-configured wafers to a Si carrier. Electrical test shows good connectivity between front and back side RDL with Cu TMV, thus enabling embedding wafer level package for PoP application.