Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier

被引：81
|
作者：
Chang, DY [1 ]
机构：
[1] Texas Instruments Inc, Tucson, AZ 85706 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2004年 / 51卷 / 11期
关键词：
amplifier; analog-digital (A/D) conversion; aperture error; digital correction; low power; sample-and-hold amplifier (SHA); time constant;
D O I：
10.1109/TCSI.2004.836842
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Design techniques for a low-power pipelined analog-to-digital converters (ADCs) without using a front-end sample-and-hold amplifier are presented. Two sampling topologies are compared that minimize aperture error by matching the time constant between signal paths. A digital correction expansion technique is also presented for multibit ADCs, which further increases tolerance to aperture error. Elimination of the front-end SHA can save more than half of the ADCs static power dissipation.
引用
收藏
页码：2123 / 2132
页数：10
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