Design techniques for a pipelined ADC without using a front-end sample-and-hold amplifier

被引：81
|
作者：
Chang, DY [1 ]
机构：
[1] Texas Instruments Inc, Tucson, AZ 85706 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2004年 / 51卷 / 11期
关键词：
amplifier; analog-digital (A/D) conversion; aperture error; digital correction; low power; sample-and-hold amplifier (SHA); time constant;
D O I：
10.1109/TCSI.2004.836842
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Design techniques for a low-power pipelined analog-to-digital converters (ADCs) without using a front-end sample-and-hold amplifier are presented. Two sampling topologies are compared that minimize aperture error by matching the time constant between signal paths. A digital correction expansion technique is also presented for multibit ADCs, which further increases tolerance to aperture error. Elimination of the front-end SHA can save more than half of the ADCs static power dissipation.
引用
收藏
页码：2123 / 2132
页数：10
相关论文
共 50 条
  • [21] Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC
    Chen Z.
    Wei J.
    Qian H.
    Yu Z.
    Su X.
    Xue Y.
    Zhang H.
    Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology, 2019, 41 (03): : 732 - 738
  • [22] Analysis and design of a boost PFC converter with sample-and-hold control techniques
    Wang, Jian-Min
    Chien, Hung-Chun
    Wu, Sen-Tung
    Yen, Shang-Chin
    Lin, Jing-Yuan
    INTERNATIONAL TRANSACTIONS ON ELECTRICAL ENERGY SYSTEMS, 2015, 25 (11): : 3122 - 3138
  • [23] A 12-bit 100 MS/s pipelined ADC without using front-end SHA (vol 86, pg 142, 2018)
    Imanpoor, H.
    Mehranpouy, M.
    Torkzadeh, P.
    Jannesari, A.
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2018, 88 : 174 - 174
  • [24] RF Receiver Front-End and Pipelined Analog to Digital Chip Design
    Lai, Wen-Cheng
    2021 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS-ASIA (ICCE-ASIA), 2021,
  • [25] Highly Linear Noise-Shaped Pipelined ADC Utilizing a Relaxed Accuracy Front-End
    Rajaee, Omid
    Moon, Un-Ku
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (02) : 502 - 515
  • [26] NEW CHROMA-PROCESSING IC USING SAMPLE-AND-HOLD TECHNIQUES
    HARWOOD, LA
    IEEE TRANSACTIONS ON BROADCAST AND TELEVISION RECEIVERS, 1973, BT19 (02): : 136 - 141
  • [27] Design of a Programmable Biomedical Front-End Amplifier with Pseudo Resistors
    Leung, Fu-Shing
    Liu, Don-Gey
    Lai, Weidian
    Shiau, Miin-Shyue
    Wu, Hong-Chong
    Zheng, Ziwei
    2019 8TH INTERNATIONAL SYMPOSIUM ON NEXT GENERATION ELECTRONICS (ISNE), 2019,
  • [28] A new technique for designing high performance front-end Sample and Hold circuits
    Chouia, Y
    El-Sankary, K
    Saleh, A
    Sawan, M
    Ghannouchi, F
    16TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, PROCEEDINGS, 2004, : 16 - 19
  • [29] Improve the design of your passive wideband ADC front-end network
    Reeder, Rob
    Electronic Design, 2010, 58 (04) : 50 - 55
  • [30] A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC
    Chen, Chi-Wei
    Su, Chien-Yu
    Chen, Hsin-Shu
    2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22), 2022, : 3483 - 3487
12345