Sample and Hold Front-end Circuit for 14-bit 210 MS/s Charge-domain ADC

被引：0
|
作者：
Chen Z. [1 ,2 ]
Wei J. [2 ]
Qian H. [2 ]
Yu Z. [2 ,3 ]
Su X. [2 ,3 ]
Xue Y. [2 ]
Zhang H. [4 ]
机构：
[1] School of Information Engineering, Huangshan University, Huangshan
[2] No.58 Research Institute, China Electronic Technology Group Corporation, Wuxi
[3] Microelectronic Institute, Xidian University, Xi'an
[4] School of Microelectronic, Xi'an Jiaotong University, Xi'an
来源：
Dianzi Yu Xinxi Xuebao/Journal of Electronics and Information Technology | 2019年 / 41卷 / 03期
基金：
中国国家自然科学基金;
关键词：
Charge-domain; Common-mode charge; Low power; Pipelined Analog-to-Digital Converter (ADC); Sample and hold;
D O I：
10.11999/JEITdzyxxxb-41-3-732
中图分类号：
学科分类号：
摘要：
A high precision common mode level insensitive sample and hold front-end circuit for charge domain pipelined Analog-to-Digital Converter (ADC) is proposed. The sample and hold circuit can be used to compensate the common mode charge errors caused by the variation of input common mode level in charge domain pipelined ADCs. Based on the proposed sample and hold circuit, a 14-bit 210 MS/s charge domain pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show the 14-bit 210 MS/s ADC achieves the signal-to-noise ratio of 71.5 dBFS and the spurious free dynamic range of 85.4 dBc, with 30.1 MHz input single tone signal at 210 MS/s, while the ADC core consumes the power consumption of 205 mW and occupies an area of 3.2 mm2. © 2019, Science Press. All right reserved.
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页码：732 / 738
页数：6
相关论文
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