A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC

被引:0
|
作者
Liu, Yu [1 ]
Shen, Yupeng [1 ]
Chen, Mingliang [1 ]
Xu, Hui [1 ]
Chen, Xubin [1 ]
Liu, Jiarui [1 ]
Wang, Zhiyu [1 ]
Yu, Faxin [1 ]
机构
[1] Zhejiang Univ, Sch Aeronaut & Astronaut, Hangzhou 310027, Peoples R China
关键词
Gain; Capacitors; Bandwidth; Switches; System-on-chip; Simulation; Resistance; Feedback amplifier (FA); gain-boosted cascode amplifier (GBCA); phase margin (PM); pipelined analog-to-digital converter (ADC); three-layer cascode structure; BACKGROUND CALIBRATION; SKEW;
D O I
10.1109/TVLSI.2024.3439374
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this brief, a high-gain and wide-bandwidth single-stage gain-boosted cascode amplifier (GBCA) is proposed for the front-end sample-and-hold amplifier (SHA) in 14-bit 2.5-GS/s pipelined analog-to-digital converter (ADC). This GBCA is composed of a two-layer main cascode amplifier and a three-layer cascode feedback amplifier (FA). The three-layer cascode structure introduces more than 20-dB gain enhancement compared with conventional two-layer FAs. However, adjacent poles appear near the gain bandwidth product (GBW) of the three-layer cascode FA, which may seriously deteriorate the phase margin (PM) of the FA and further prolong the settling time of closed-loop GBCA. A PM expansion technique is proposed to improve the PM of FA by adding a group of switched capacitor array. At the same time, the open-loop GBCA achieves 104-dB direct-current (dc) gain and 65.2-GHz GBW, which satisfies the harsh requirements of the ping-pong interleaved SHA with 12-dB gain on-chip. The pipelined ADC fabricated in 28-nm CMOS process consumes 554 mW at 2.5-GS/s sampling rate, while achieves a signal-to-noise-and-distortion ratio (SNDR) of 52.5 dB and a spurious free dynamic range (SFDR) of 86.4 dBc with 161-MHz input signal.
引用
收藏
页码:47 / 51
页数:5
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