Analysis of various adder circuits in Deep Submicron Process.

被引：0

作者：

Aphale, Sayli S. ^{[1
]}

Fakir, Kausar ^{[1
]}

Kodagali, Sushama ^{[1
]}

Mande, S. S. ^{[1
]}

机构：

[1] Ramrao Adik Inst Technol, Elect Engn, Nerul, Navi Mumbai, India

来源：

2016 INTERNATIONAL CONFERENCE ON AUTOMATIC CONTROL AND DYNAMIC OPTIMIZATION TECHNIQUES (ICACDOT) | 2016年

关键词：

Adder; power-delay-product; parasitic capacitance; Electric tool; LT spice;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Adder is the most fundamental and frequently used operational circuit in digital electronic systems. Designing, implementation and analysis of the single bit full adder circuits in 45nm deep sub-micron process is the main focus of this paper. CMOS logic is used to implement the Boolean equations of the adders. Adders under consideration are Conventional adder, Mirror Adder and Transmission gate adder. Evaluation of reduction in propagation delay, power consumption, parasitic capacitance due to reduction in number of transistors analyzed. The adders are modeled using Electric tool and LT spice simulation softwares.

引用

页码：307 / 311

页数：5

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