Competitive and Cost Effective high-k based 28nm CMOS Technology for Low Power Applications

被引：0
|
作者：
Arnaud, F.
Thean, A.
Eller, M.
Lipinski, M.
Teh, Y. W.
Ostermayr, M.
Kang, K.
Kim, N. S.
Ohuchi, K.
Han, J-P.
Nair, D. R.
Lian, J.
Uchimura, S.
Kohler, S.
Miyaki, S.
Ferreira, P.
Park, J-H.
Hamaguchi, M.
Miyashita, K.
Augur, R.
Zhang, Q.
Strahrenberg, K.
ElGhouli, S.
Bonnouvrier, J.
Matsuoka, F.
Lindsay, R.
Sudijono, J.
Johnson, F. S.
Ku, J. H.
Sekine, M.
Steegen, A.
Sampson, R.
机构：
来源：
2009 IEEE INTERNATIONAL ELECTRON DEVICES MEETING | 2009年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we present a cost-effective 28nm CMOS technology for low power (LP) applications based on a high-k, single-metal-gate-first architecture. We report raw gate densities up to 4200 kGate/mm(2), and, using the ARM Cortex-R4F as a reference, we report achievement of an overall 2.4x area reduction in 28nm from 45nm technology. Our high-density SRAM bit-cell (area= 0.120mm(2)) has a demonstrated Static Noise Margin (SNM) of 213mV at IV. Fully compatible with power/leakage management techniques intensively used in low power designs, the transistor drive currents are increased +35% & +10%, for nFET and pFET respectively, with respect to a 28nm LP poly/SiON reference [3]. Compatible with LP system-on-chip requirements, ultra low-cost, high performance analog devices are reported which leverage a dramatic improvement in matching factor (AVT similar to 2mV.um) versus our previously-reported result [2]. An optimized interconnection scheme based on Extreme Low k (ELK) dielectric (k similar to 2.4) and advanced metallization allows high density wiring with competitive R-C versus our previous technology.
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页码：603 / 606
页数：4
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