Digital background calibration of pipeline ADC with open-loop gain stage

被引：0
|
作者：
Tavassoli, B. [1 ]
Shoaei, O. [1 ]
机构：
[1] Univ Tehran, IC Design Lab, Dept ECE, Tehran, Iran
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/ISCAS.2006.1693818
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this work, a digital background calibration method for pipelined ADC is proposed which can compensate for the nonlinearity in amplifier gain. The proposed scheme is based on input statistical distribution property which is assumed to be known. The error correction is completely performed in digital domain. In analog domain it is only necessary to add two comparators for generating calibration threshold. Results show an improvement of 16 dB in SNDR for a nonlinear gain stage designed in a 1.5 V supply and 0.35 mu m CMOS Technology.
引用
收藏
页码：5255 / +
页数：2
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