An open source synthesisable model in VHDL of a 64-bit MIPS-based processor

被引：0

作者：

Kelly, Daniel R. ^{[1
]}

Phillips, Braden J. ^{[1
]}

Al-Sarawi, Said ^{[1
]}

机构：

[1] Univ Adelaide, Ctr High Performance Integrated Technol & Syst CH, Adelaide, SA 5005, Australia

来源：

SMART STRUCTURES, DEVICES, AND SYSTEMS III | 2007年 / 6414卷

关键词：

arithmetic; VHDL; open source; synthesis; MIPS; computer architecture; speculation; pipeline; processor model; VLSI;

D O I：

10.1117/12.695580

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

This report describes an open source VHDL description of a 64-bit MIPS-based processor. The pipeline can execute most instructions from the MIPS III instruction set architecture (ISA). The full pipeline is made available to digital VLSI engineers as a platform to test cell designs as a part of a complete computing system. The pipeline is an 8-stage RISC based on the MIPS R4000 series of processors, and includes common arithmetic operations on 32- and 64-bit operands, and full IEEE 754 floating point support. This report describes the architecture and components of the MIPS-based processor.

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页数：9

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