A 1-GS/s 6-bit Flash ADC in 90 nm CMOS

被引：4

作者：

Shaker, Mohamed O. ^{[1
]}

Gosh, Soumik ^{[1
]}

Bayoumi, Magdy A. ^{[1
]}

机构：

[1] Univ Louisiana Lafayette, Ctr Adv Comp Studies, Lafayette, LA 70504 USA

来源：

2009 52ND IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 2009年

关键词：

A/D CONVERTER; DIGITAL CMOS;

D O I：

10.1109/MWSCAS.2009.5236133

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. HSpice simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.

引用

页码：144 / 147

页数：4

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