An implementation of 2D IDCT using AltiVec

被引：0
|
作者：
Lu, SJ [1 ]
Zhang, J [1 ]
Zhang, X [1 ]
Zhao, CJ [1 ]
机构：
[1] Motorola Australian Res Ctr, Sydney, NSW 1455, Australia
来源：
2002 6TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING PROCEEDINGS, VOLS I AND II | 2002年
关键词：
AltiVec; pre-scaling for IDCT; SIMD parallel processing and data manipulation;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper explores the key functions of AltiVec through an implementation of 2D IDCT algorithm. By providing a benchmark for video processing, the advantage of using SIMD-style of parallel processing technique has been demonstrated. Besides a variety of instructions available for parallel arithmetic computations, a solution for efficiently reorganising data for parallel processing is also provided by AltiVec. The implementation resulted in a speedup of 10 times compared to its scalar version.
引用
收藏
页码：17 / 20
页数：4
相关论文
共 50 条
  • [31] Implementation of the 2D DCT using a Xilinx XC6264 FPGA
    Trainor, DW
    Heron, JP
    Woods, RF
    SIPS 97 - 1997 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: DESIGN AND IMPLEMENTATION, 1997, : 541 - 550
  • [32] Efficient diagonal data mapping for large size 2D DCT/IDCT using single port SRAM based transpose memory
    Revathi, K. G.
    Malar, J. Reeja
    2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 4894 - 4898
  • [33] High-level Synthesized 2-D IDCT/IDST Implementation for HEVC Codecs on FPGA
    Viitamaki, Vili
    Sjovall, Panu
    Vanne, Jarno
    Hamalainen, Timo D.
    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017, : 385 - 388
  • [34] An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core
    Yang, Y
    Wang, CY
    Ahmad, MO
    Swamy, MNS
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS, 2002, : 763 - 766
  • [35] Hardware Implementation of 1D DCT/IDCT for WLAN Channel Estimation
    Diallo, Moussa
    Cariou, Laurent
    Helard, Maryline
    2013 INTERNATIONAL CONFERENCE ON COMPUTER APPLICATIONS TECHNOLOGY (ICCAT), 2013,
  • [36] A Novel Approach for and Efficient Implementation of 2 Level 2D DWT using ASIC and FPGA
    Vijay, Parvatham
    Gopalakrishnan, Seetharaman
    2013 1ST INTERNATIONAL CONFERENCE ON EMERGING TRENDS AND APPLICATIONS IN COMPUTER SCIENCE (ICETACS), 2013, : 242 - 247
  • [37] FPGA Implementation of 1D and 2D DWT architecture using modified lifting scheme
    Nagabushanam, M.
    Ramachandran, S.
    Kumar, P.
    WSEAS Transactions on Signal Processing, 2013, 9 (04): : 227 - 236
  • [38] gpuSPHASE-A shared memory caching implementation for 2D SPH using CUDA
    Winkler, Daniel
    Meister, Michael
    Rezavand, Massoud
    Rauch, Wolfgang
    COMPUTER PHYSICS COMMUNICATIONS, 2017, 213 : 165 - 180
  • [39] Implementation and comparison of reconstruction algorithms for 2D optoacoustic tomography using a linear array
    Modgil, Dimple
    La Riviere, Patrick J.
    PHOTONS PLUS ULTRASOUND: IMAGING AND SENSING 2008: THE NINTH CONFERENCE ON BIOMEDICAL THERMOACOUSTICS, OPTOACOUSTICS, AND ACOUSTIC-OPTICS, 2008, 6856
  • [40] Implementation of Swarm Based Gain Scheduling for 2D Inverted Pendulum using PLC
    Howimanpom, Suppachai
    Chookaew, Sasithom
    Sootkaneung, WarM
    2018 7TH INTERNATIONAL CONGRESS ON ADVANCED APPLIED INFORMATICS (IIAI-AAI 2018), 2018, : 630 - 633
12345