IC design of optimal four-bit Absolute value Detector based on CMOS process

被引：0
|
作者：
Xia, Haihang [1 ]
Xiang, Nianyi [2 ]
Zhao, Mingzhe [3 ]
机构：
[1] Hefei Univ Technol, HFUT, Sch Microelect, Hefei, Peoples R China
[2] South China Univ Technol, SCUT, Sch Automat Sci & Engn, Guangzhou, Peoples R China
[3] Xi An Jiao Tong Univ, XJTU, Sch Elect Engn, Xian, Peoples R China
来源：
4TH INTERNATIONAL CONFERENCE ON INFORMATICS ENGINEERING AND INFORMATION SCIENCE (ICIEIS2021) | 2022年 / 12161卷
关键词：
absolute-value detector; mirror adder; gate sizing; minimum energy consumption;
D O I：
10.1117/12.2627202
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Design and implement a high-performance absolute-value detector through the CMOS process, and realize the function of taking the absolute value of the input data and then comparing it, which can be applied in a variety of circuits, such as A/D conversion. The circuit structure is simple, which adopts the structure of the mirror adder and the multiplexer. This paper also looks for the critical path and uses logical effort theory to find the minimum delay. The next work is to adjust the gate size and determine the optimal size of the device and the optimal power supply voltage. Finally, this paper attempts to achieve the minimum energy consumption.
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收藏
页数：14
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