An efficient hardware implementation of a novel unary Spiking Neural Network multiplier with variable dendritic delays

被引:25
|
作者
Diaz, Carlos [1 ]
Sanchez, Giovanny [1 ]
Duchen, Gonzalo [1 ]
Nakano, Mariko [1 ]
Perez, Hector [1 ,2 ]
机构
[1] Inst Politecn Nacl, Ave Santa Ana 1000, Mexico City 04430, DF, Mexico
[2] ESIME Culhuacan, Mexico City, DF, Mexico
关键词
FPGA; Unary multiplier; Dendritic delays; Neuromorphic;
D O I
10.1016/j.neucom.2015.12.086
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
We propose a novel unary spiking circuit for a serial multiplier with variable dendritic delays. Serial multipliers commonly use the soma model for the arithmetic operation. The structure of the serial multiplier and the efficient implementation of the dendritic delays on customized neuromorphic hardware are the major contributions of this work. The design of the multiplier was inspired by the biological processes of dendrites, which use feedback connections and dendritic growth to synchronize the neural processing performed by the soma. The multiplier eliminates complex rules by adopting the soma model with dendritic connectivity configurations, increasing the processing speed compared with previously reported solutions based on Spiking Neural Networks. (C) 2016 Elsevier B.V. All rights reserved.
引用
收藏
页码:130 / 134
页数:5
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