LVTSCR structures for latch-up free ESD protection of BiCMOS RF circuits

被引：11
|
作者：
Vashchenko, V [1 ]
Concannon, A [1 ]
ter Beek, M [1 ]
Hopper, P [1 ]
机构：
[1] NSC, Santa Clara, CA 95052 USA
来源：
MICROELECTRONICS RELIABILITY | 2003年 / 43卷 / 01期
关键词：
D O I：
10.1016/S0026-2714(02)00125-7
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The results of a numerical and experimental study aimed at increasing the holding on-state voltage of a low-voltage triggered silicon controlled rectifier are presented. Using TCAD numerical simulations two solutions are presented that are based on emitter injection control by the modification of the emitter-drain area ratio and by the addition of internal diodes in the emitter line. Experimental data generated in a 0.18 mum CMOS technology demonstrate the effectiveness of the new low-voltage triggered silicon controlled rectifier (LVTSCR) structures and validates the simulation results. It has been demonstrated that for the LVTSCR structures with high holding voltage the electrostatic discharge efficiency is 3-5 times higher than that of a conventional grounded gate snapback NMOS and simultaneously has 50% lower RF load capacitance. (C) 2002 Elsevier Science Ltd. All rights reserved.
引用
收藏
页码：61 / 69
页数：9
相关论文
共 50 条
  • [21] Effects of ESD protections on latch-up sensitivity of CMOS 4-stripe structures
    Pavan, P
    Pellesi, A
    Meneghesso, G
    Zanoni, E
    MICROELECTRONICS AND RELIABILITY, 1997, 37 (10-11): : 1561 - 1564
  • [22] ESD robustness concern for SOI-LIGBTs with typical latch-up immunity structures
    Ye, Ran
    Liu, Siyang
    Sun, Weifeng
    Hou, Bo
    SOLID-STATE ELECTRONICS, 2017, 137 : 6 - 9
  • [23] Latch-up ring design guidelines to improve electrostatic discharge (ESD) protection scheme efficiency
    Trémouilles, D
    Bafleur, M
    Bertrand, G
    Nolhier, N
    Mauran, N
    Lescouzères, L
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (10) : 1778 - 1782
  • [24] Triggering of Transient Latch-up (TLU) by System Level ESD
    Brodbeck, Tilo
    Stadler, Wolfgang
    Baumann, Christian
    Esmark, Kai
    Domanski, Krzysztof
    ELECTRICAL OVERSTRESS/ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS 2010, 2010,
  • [25] HV Latch-up at System Level ESD Current Injection
    Marreiro, David
    Vashchenko, Vladislav
    2019 41ST ANNUAL EOS/ESD SYMPOSIUM (EOS/ESD), 2019,
  • [26] ElectroStatic discharges (ESD), latch-up and pad design constraints
    Salome, P
    Richier, C
    MICROELECTRONIC ENGINEERING, 1999, 49 (1-2) : 83 - 94
  • [27] Triggering of Transient Latch-up by System-Level ESD
    Brodbeck, Tilo
    Stadler, Wolfgang
    Baumann, Christian
    Esmark, Kai
    Domanski, Krzysztof
    IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2011, 11 (04) : 509 - 515
  • [28] LATCH-UP FREE VLSI CMOS CIRCUITS CONSIDERING POWER-ON TRANSIENTS
    RECZEK, W
    WINNERL, J
    PRIBYL, W
    JOURNAL DE PHYSIQUE, 1988, 49 (C-4): : 49 - 52
  • [29] LATCH-UP ELIMINATION IN BULK CMOS LSI CIRCUITS
    SCHROEDER, JE
    OCHOA, A
    DRESSENDORFER, PV
    IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 1980, 27 (06) : 1735 - 1738
  • [30] THE BEHAVIOR OF BILATERAL LATCH-UP TRIGGERING IN VLSI ELECTROSTATIC DISCHARGE DAMAGE PROTECTION CIRCUITS
    HUANG, HS
    CHANG, CY
    HSU, CC
    CHEN, KL
    LIN, JK
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1993, 32 (11A): : 4928 - 4933
12345