Detailed and Highly Parallelizable Cycle-Accurate Network-on-Chip Simulation on GPGPU

被引：0

作者：

Charif, Amir ^{[1
]}

Coelho, Alexandre ^{[1
]}

Zergainoh, Nacer-Eddine ^{[1
]}

Nicolaidis, Michael ^{[1
]}

机构：

[1] Univ Grenoble Alpes, TIMA Lab, Grenoble, France

来源：

2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2017年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250x, while offering RTL-like accuracy. These promising results make our simulation method ideal for evaluating future NoCs comprising thousands of nodes.

引用

页码：672 / 677

页数：6

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