RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

被引：17

作者：

Cadix, L. ^{[1
,2
]}

Bermond, C. ^{[2
]}

Fuchs, C.

Farcy, A. ^{[1
]}

Leduc, P. ^{[3
]}

DiCioccio, L. ^{[3
]}

Assous, M. ^{[3
]}

Rousseau, M. ^{[1
,3
]}

Lorut, F. ^{[1
]}

Chapelon, L. L. ^{[1
]}

Flechet, B. ^{[2
]}

Sillon, N. ^{[3
]}

Ancey, P. ^{[1
]}

机构：

[1] STMicroelectronics, F-38926 Crolles, France

[2] Univ Savoie, IMEP, LAHC, F-73376 Le Bourget Du Lac, France

[3] CEA, Leti, F-38054 Grenoble, France

来源：

MICROELECTRONIC ENGINEERING | 2010年 / 87卷 / 03期

关键词：

TSV; Electrical properties; Modelling; 3D integration;

D O I：

10.1016/j.mee.2009.08.026

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 mu m wide and 15 mu m deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible pi-shaped analytical parametrical model of the TSV. (C) 2009 Elsevier B.V. All rights reserved.

引用

页码：491 / 495

页数：5

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