Combined subthreshold and gate-oxide leakage power reduction in deep-submicron CMOS circuits

In this work we present a methodology for minimizing simultaneously the subthreshold mid the gate-tunneling currents in CMOS combinatorial circuits. We use a simple method for estimating the total leakage in a circuit based on the knowledge of primary input signal probabilities in conjunction with state-dependent leakage tables. We take advantage of the state-dependence exhibited by the leakage currents to reduce the total leakage in a circuit through pin reordering and the application of low-leakage standby input vectors. Pin reordering is done on a per-vector basis for known input probabilities, mid on a statistical basis for unknown input probabilities. Results are given for a number of ISCAS-85 benchmark circuits for different gate-oxide thicknesses.