Experimental comparison between Double Gate, Ground Plane, and Single Gate SOICMOSFETs

被引：20

作者：

Lolivier, J ^{[1
]}

Widiez, J ^{[1
]}

Vinet, M ^{[1
]}

Poiroux, T ^{[1
]}

Daugé, F ^{[1
]}

Previtali, B ^{[1
]}

Mouis, M ^{[1
]}

Jommah, J ^{[1
]}

Balestra, F ^{[1
]}

Deleonibus, S ^{[1
]}

机构：

[1] CEA, DRT, LETI, F-38054 Grenoble 9, France

来源：

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSDER.2004.1356492

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we report an experimental comparison between planar Double Gate, Single Gate and Ground Plane CMOSFETs. Thanks to an original process, we managed to co-integrate on the same wafer these three devices with a TiN metal gate. Short channel effect control, static performance and mobility are quantified for each architecture. Advantages of Double Gate devices over Ground plane and Single Gate transistors are experimentally highlighted. Ground Plane MOSFETs require an optimized BOX in order to achieve a 30% in the saturation current.

引用

页码：77 / 80

页数：4

共 50 条

[1] A Comparison of Dual Material Double Gate JLFET with Single Material Double Gate JLFET
Kumar, Ajay
Chaudhry, Amit
Kumar, Vijay
Sharma, Vishal
PROCEEDINGS ON 2016 2ND INTERNATIONAL CONFERENCE ON NEXT GENERATION COMPUTING TECHNOLOGIES (NGCT), 2016, : 99 - 102
[2] A comparison study between double and single gate p-IMOS
Hassani, F. A.
Fathipour, A.
Mehran, M.
2007 AFRICON, VOLS 1-3, 2007, : 573 - 578
[3] Experimental gate misalignment analysis on double gate SOI MOSFETs
Widiez, J
Daugé, F
Vinet, M
Poiroux, T
Previtali, B
Mouis, M
Deleonibus, S
2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, : 185 - 186
[4] RF and noise performance of double gate and single gate SOI
Lazaro, A.
Iniguez, B.
SOLID-STATE ELECTRONICS, 2006, 50 (05) : 826 - 842
[5] A Model of the Gate Capacitance of Surrounding Gate Transistors: Comparison With Double-Gate MOSFETs
Garcia Ruiz, Francisco J.
Maria Tienda-Luna, Isabel
Godoy, Andres
Donetti, Luca
Gamiz, Francisco
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (10) : 2477 - 2483
[6] Comparison between the dynamic performance of double- and single-gate AlInAs/InGaAs HEMTs
Vasallo, Beatriz G.
Wichmann, Nicolas
Bollaert, Sylvain
Roelens, Yannick
Cappy, Alain
Gonzalez, Tomas
Pardo, Daniel
Mateos, Javier
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (11) : 2815 - 2822
[7] Experimental comparison between sub-0.1-μm ultrathin SOI single- and double-gate MOSFETs:: Performance and mobility
Widiez, Julie
Poiroux, Thierry
Vinet, Maud
Mouis, Mireille
Deleonibus, Simon
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2006, 5 (06) : 643 - 648
[8] Comparison between the noise performance of double- and single-gate InP-based HEMTs
Vasallo, Beatriz G.
Wichmann, Nicolas
Bollaert, Sylvain
Roelens, Yannick
Cappy, Alain
Gonzalez, Tomas
Pardo, Daniel
Mateos, Javier
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (06) : 1535 - 1540
[9] Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study
Gupta, Divyam
Bagga, Navjeet
Dasgupta, S.
2018 CONFERENCE ON EMERGING DEVICES AND SMART SYSTEMS (ICEDSS), 2018, : 110 - 112
[10] Different Ground Plane (GP) Architectures on 25 nm Single-Gate (SG) versus Double-Gate (DG) UTBB SOI MOSFETs from Analog and RF Perspectives
Othman, Noraini
Arshad, M. K. Md
Sabki, S. N.
JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2017, 12 (04) : 392 - 399

← 1 2 3 4 5 →