Experimental comparison between Double Gate, Ground Plane, and Single Gate SOICMOSFETs

被引：20

作者：

Lolivier, J ^{[1
]}

Widiez, J ^{[1
]}

Vinet, M ^{[1
]}

Poiroux, T ^{[1
]}

Daugé, F ^{[1
]}

Previtali, B ^{[1
]}

Mouis, M ^{[1
]}

Jommah, J ^{[1
]}

Balestra, F ^{[1
]}

Deleonibus, S ^{[1
]}

机构：

[1] CEA, DRT, LETI, F-38054 Grenoble 9, France

来源：

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年

关键词：

D O I：

10.1109/ESSDER.2004.1356492

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, we report an experimental comparison between planar Double Gate, Single Gate and Ground Plane CMOSFETs. Thanks to an original process, we managed to co-integrate on the same wafer these three devices with a TiN metal gate. Short channel effect control, static performance and mobility are quantified for each architecture. Advantages of Double Gate devices over Ground plane and Single Gate transistors are experimentally highlighted. Ground Plane MOSFETs require an optimized BOX in order to achieve a 30% in the saturation current.

引用

页码：77 / 80

页数：4

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