Effect of spacer scaling on PMOS transistors

被引：0

作者：

Lau, Wai Shing ^{[1
]}

Eng, Chee Wee ^{[2
]}

Vigar, David ^{[2
]}

Chan, Lap ^{[2
]}

Siah, Soh Yun ^{[2
]}

机构：

[1] Nanyang Technol Univ, Sch EEE, Block S2-1,Nanyang Ave, Singapore 639798, Singapore

[2] Chartered Semicond Mfg Ltd, Singapore 738406, Singapore

来源：

TRANSISTOR SCALING- METHODS, MATERIALS AND MODELING | 2006年 / 913卷

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Our observation is that both the on-current and off-current of state-of-the-art p-channel MOS transistors tend to become larger when the L-shaped spacer becomes smaller due to two different mechanisms: a decrease in the effective channel length Leff (Mechanism A) and a decrease in the series resistance (Mechanism B). In our analysis, we use drain induced barrier lowering (DIBL) as a measure of Leff and we assume that there is a linear relationship between the on-current, the logarithm of the off current and DIBL. Our assumption is supported by our theoretical derivations.

引用

页码：93 / +

页数：2

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