Top-down PLL design methodology combining block diagram, behavioral, and transistor-level simulators

被引：2

作者：

Nicolle, B. ^{[1
,2
]}

Tatinian, W. ^{[1
]}

Mayol, J. -J. ^{[2
]}

Oudinot, J.

Jacquemod, G. ^{[1
]}

机构：

[1] UNSA, CNRS, UMR 6071, LEAT, 250 Rue Albert Einstein, F-06560 Valbonne, France

[2] Mentor Graph Corp, F-38334 Saint Ismier, France

来源：

2007 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2007年

关键词：

circuit simulation; simulation software; design methodology;

D O I：

10.1109/RFIC.2007.380927

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present a design methodology based on a multi-simulator approach instead of using co-simulation. We based our study on a Phase Locked Loop (PLL) used in RF transceivers for frequency synthesis. We used Simulink as block diagram simulator, ADVance MS (ADMS) as behavioral simulator and Eldo as transistor-level simulator. The proposed results show the accuracy and simulation time for each description level.

引用

页码：475 / +

页数：2

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