Sleepy stack reduction of leakage power

Leakage power consumption of current CMOS technology is already a great challenge. ITRS projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. We propose a novel leakage reduction technique, named "sleepy stack," which can be applied to general logic design. Our sleepy stack approach retains exact logic state - making it better than traditional sleep and zigzag techniques - while saving leakage power consumption. Unlike the stack approach (which saves state), the sleepy stack approach can work well with dual-V-th technologies, reducing leakage by several orders of magnitude over the stack approach in single-V-th technology. Unfortunately, the sleepy stack approach does have a area penalty (roughly 50similar to120%) as compared to stack technology; nonetheless, the sleepy stack approach occupies a niche where state-saving and extra low leakage is desired at a (potentially small) cost in terms of increased delay and area.