Design and optimization of multi-level TAM architectures for hierarchical SOCs

被引：15

作者：

Iyengar, V ^{[1
]}

Chakrabarty, K ^{[1
]}

Krasniewski, MD ^{[1
]}

Kumar, GN ^{[1
]}

机构：

[1] IBM Microelect, Essex Jct, VT 05452 USA

来源：

21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/VTEST.2003.1197667

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Multi-level TAM optimization is necessary for modular testing of hierarchical SOCs that contain older-generation SOCs as embedded cores. We present two hierarchical TAM optimization flows that exploit recent advances in TAM design for flattened SOC hierarchies. Unlike prior methods that assume flat test hierarchies, the proposed methods are directly applicable to real-world design transfer models between the core vendor and the SOC integrator Experimental results are presented for four ITC'02 SOC Test Benchmarks.

引用

页码：299 / 304

页数：6

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