Design of high performance double edge-triggered flip-flops

被引：7

作者：

Mishra, SM ^{[1
]}

Rofail, SS ^{[1
]}

Yeo, KS ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Singapore 639798, Singapore

来源：

IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS | 2000年 / 147卷 / 05期

关键词：

D O I：

10.1049/ip-cds:20000672

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A methodology for constructing double edge-triggered flip-flops (DETFFs) from existing latches, which removes the need for complete flip-flops or the presence of docked nodes in the combining section is presented. The application of this methodology to designing DETFFs based on latches constructed from pass transistor/transmission gates, true single-phase clocked structures, and differential logic is investigated. The resulting DETFFs deliver high performance and do not suffer from the problems of charge sharing, charge coupling, reduced voltage swing, poor supply voltage scaling properties, and excessive power dissipation plaguing existing DETFFs.

引用

页码：283 / 290

页数：8

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