A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

被引：906

作者：

Liu, Chun-Cheng ^{[1
]}

Chang, Soon-Jyh ^{[1
]}

Huang, Guan-Ying ^{[1
]}

Lin, Ying-Zu ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2010年 / 45卷 / 04期

关键词：

Analog-to-digital converter; energy efficient; low power; successive approximation register;

D O I：

10.1109/JSSC.2010.2042254

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-mu m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 x 265 mu m(2).

引用

页码：731 / 740

页数：10

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