Simplified double switching SVPWM implementation for three-level VSI

A generalised space vector pulse width modulation (SVPWM) framework for the realisation of all double switching states with a memory-optimised method is proposed to reduce the total harmonic distortion (THD) and to provide neutral point voltage balancing for three-level NPC voltage source inverter (VSI). The proposal provides an efficient SVPWM implementationwith reduced hardware requirement and zero increase in software complexity in comparison to the existing schemes. Microcontroller analogue-to-digital converter (ADC) hardware replaces multichannel ADC and associated Field programmable gate array hardware in this proposal. The proposed method follows digital control architecture and eliminates the need to sample phase voltages separately. The proposed algorithm samples rms voltage of one phase and generates eight bit modulation index command by a suitable compensation algorithm. The implemented SVPWM algorithm takes the modulation index command value and generates phase voltage values by multiplying with the stored sine angle values. Gate pulses are generated in the proposed implementation by the hardware pulse width modulation (PWM) block and there is no need for digital-to-analogue converter. The proposed strategy is validated with a fundamental frequency of 50 Hz on a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI using low-cost PIC microcontroller. The superiority of the proposed method lies in providing an efficient three-level SVPWM implementation with reduced THD, neutral point voltage balancing, reduced hardware requirement, small lookup table and zero increase in the software computing overhead.