High Hole Mobility in Multiple Silicon Nanowire Gate-All-Around pMOSFETs on (110) SOI

被引:0
|
作者
Chen, Jiezhi [1 ]
Saraya, Takuya [1 ]
Hiramoto, Toshiro [1 ]
机构
[1] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan
关键词
STRAINED-SI; ENHANCEMENT; DEPENDENCE; TRANSPORT; MOSFETS;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Systematic study on hole mobility in gate-all-around (GAA) multiple Si nanowire (NW) pFETs on (110) SOI is presented for the first time. [110]-NWs show high mobility, 2.4x enhancement over universal (100) mobility, even in high N-inv region and in narrow (25nm) NWs. Furthermore, effects of uniaxial tensile stress are also investigated, indicating that [110] direction uniaxial stress is effective to modulate hole mobility in NWs.
引用
收藏
页码:90 / 91
页数:2
相关论文
共 50 条
  • [1] Impact of the channel doping on the low-frequency noise of gate-all-around silicon vertical nanowire pMOSFETs
    Simoen, Eddy
    Veloso, Anabela
    Matagne, Philippe
    Claeys, Cor
    [J]. SOLID-STATE ELECTRONICS, 2023, 200
  • [2] Vertical Ge Gate-All-Around Nanowire pMOSFETs With a Diameter Down to 20 nm
    Liu, Mingshan
    Scholz, Stefan
    Hardtdegen, Alexander
    Bae, Jin Hee
    Hartmann, Jean-Michel
    Knoch, Joachim
    Gruetzmacher, Detlev
    Buca, Dan
    Zhao, Qing-Tai
    [J]. IEEE ELECTRON DEVICE LETTERS, 2020, 41 (04) : 533 - 536
  • [3] Gate-all-around twin silicon nanowire SONOS memory
    Suk, Sung Dae
    Yeo, Kyoung Hwan
    Cho, Keun Hwi
    Li, Ming
    Yeoh, Yun young
    Hong, Ki-Ha
    Kim, Sung-Han
    Koh, Young-Ho
    Jung, Sunggon
    Jang, WonJun
    Kim, Dong-Won
    Park, Donggun
    Ryu, Byung-Il
    [J]. 2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 142 - +
  • [4] Fully gate-all-around silicon nanowire CMOS devices
    Singh, N.
    Buddharaju, K. D.
    Agarwal, A.
    Rustagi, S. C.
    Lo, G. Q.
    Balasubramanian, N.
    Kwong, D. L.
    [J]. SOLID STATE TECHNOLOGY, 2008, 51 (05) : 34 - 37
  • [5] Gate-All-Around Silicon Nanowire Devices: Are these the Future of CMOS?
    Lo, G. Q.
    Singh, N.
    Rustagi, S. C.
    Buddharaju, K. D.
    Balasubramanian, N.
    Kwong, D. L.
    [J]. SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES, 2008, 16 (10): : 729 - 729
  • [6] Fully gate-all-around silicon nanowire CMOS devices
    Institute of Microelectronics, Singapore, Singapore
    [J]. Solid State Technol, 2008, 5 (34-37):
  • [7] Structure effects in the gate-all-around silicon nanowire MOSFETs
    Liang, Gengchiau
    [J]. EDSSC: 2007 IEEE INTERNATIONAL CONFERENCE ON ELECTRON DEVICES AND SOLID-STATE CIRCUITS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 129 - 132
  • [8] Modeling and analysis of gate-all-around silicon nanowire FET
    Chen, Xiangchen
    Tan, Cher Ming
    [J]. MICROELECTRONICS RELIABILITY, 2014, 54 (6-7) : 1103 - 1108
  • [9] Hole Mobility Characteristics in Si Nanowire pMOSFETs on (110) Silicon-on-Insulator
    Chen, Jiezhi
    Saraya, Takuya
    Hiramoto, Toshiro
    [J]. IEEE ELECTRON DEVICE LETTERS, 2010, 31 (11) : 1181 - 1183
  • [10] Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature
    Sekiguchi, Shohei
    Ahn, Min-Ju
    Mizutani, Tomoko
    Saraya, Takuya
    Kobayashi, Masaharu
    Hiramoto, Toshiro
    [J]. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2021, 9 : 1151 - 1154