High-Speed FPGA Implementation for DWT of Lifting Scheme

被引：0
|
作者：
Wang, Wei [1 ]
Du, Zhiyun [1 ]
Zeng, Yong [1 ]
机构：
[1] Chongqing Univ Posts & Telecommun, Coll Elect Engn, Chongqing 400065, Peoples R China
来源：
2009 5TH INTERNATIONAL CONFERENCE ON WIRELESS COMMUNICATIONS, NETWORKING AND MOBILE COMPUTING, VOLS 1-8 | 2009年
关键词：
Discrete wavelet transform (DWT); lifting scheme; multi-stage pipelining; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new approach for Discrete Wavelet Transform (DWT) has been proposed recently under the name of lifting scheme. This scheme presents many advantages over the convolution-based approach. In this paper, a high speed 9/7 lifting DWT algorithm which is implementation on FPGA with multi-stage pipelining structure and rational 9/7 coefficients is presented. Compared with the architecture without multi-stage pipeline, the proposed architecture has higher operating frequency, the design raises operating frequency around 3 times more fast, at the expense of about 40% more hardware area. The hardware architecture is suitable for high speed implementation.
引用
收藏
页码：2096 / 2099
页数：4
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