NBTI reliability analysis for a 90nm CMOS technology

被引：0

作者：

Puchner, H ^{[1
]}

Hinh, L ^{[1
]}

机构：

[1] Cypress Semicond Inc, Technol R&D, San Jose, CA 95134 USA

来源：

ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2004年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a comprehensive empirical study to investigate the impact of NBTI on device performance and reliability. The NBTI lifetime is calculated for different lifetime criteria such as 10%Idsat or 50mVVt shift for different bias conditions, temperature, duty cycles, gate length, and gate width dependence to allow a true comparison between different methodologies. Finally, a circuit level implementation approach is presented to estimate the NBTI device level reliability on a circuit level. Therefore the absolute threshold voltage shift is calculated and inserted into the spice level transistor model for comer simulations.

引用

页码：257 / 260

页数：4

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