A BIST approach to on-line monitoring of digital VLSI circuits: A CAD tool

被引：1

作者：

Biswas, S ^{[1
]}

Mukhopadhyay, S ^{[1
]}

Patra, A ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Kharagpur 721302, W Bengal, India

来源：

13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/OLT.2004.1319685

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This work is concerned with the development of algorithms and CAD tools for the design of digital circuits with on line monitoring capability. An existing Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems has been adopted for on-line detection of stuck-at faults in Digital Circuits. Efficient computational techniques to deal with very large state spaces based on Ordered Binary Decision Diagrams and Abstraction have been proposed. Based on these a CAD tool has been developed that can provide a fully automated flow for design of circuits with on-line test capability without the requirement of any modification to the core and can handle generic digital circuits with cell count as high as 15,000 and having the order of 2500 states. Chips, designed using this methodology have been fabricated in 0.18-micron technology and are tested to be working.

引用

页码：184 / 189

页数：6

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