An on-line BIST technique for delay fault detection in CMOS circuits

被引：0
|
作者：
Moghaddam, Elham K. [1 ]
Hessabi, Shaahin [1 ]
机构：
[1] Sharif Univ Technol, Dept Comp Engn, Tehran, Iran
来源：
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM | 2007年
关键词：
delay fault; online testing; BIST techniques; robust delay test; design for testability;
D O I：
10.1109/ATS.2007.100
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.
引用
收藏
页码：73 / 76
页数：4
相关论文
共 50 条
  • [1] An on-line BIST technique for stuck-open fault detection in CMOS circuits
    Moghaddam, Elham K.
    Hessabi, Shaahin
    DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2007, : 619 - 625
  • [2] On-line BIST for testing analog circuits
    Velasco-Medina, J.
    Rayane, I.
    Nicolaidis, M.
    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1999, : 330 - 332
  • [3] UNIFIED TECHNIQUE FOR ON-LINE TESTING OF DIGITAL CIRCUITS: DELAY AND STUCK-AT FAULT MODELS
    Biswas, S.
    Mukhopadhyay, S.
    Patra, A.
    Sarkar, D.
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2008, 17 (06) : 1069 - 1089
  • [4] On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits
    MartinezSmith, A
    Sridhar, R
    NINTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, PROCEEDINGS, 1996, : 57 - 60
  • [5] On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
    Metra, C
    Favalli, M
    Olivo, P
    Ricco, B
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (07) : 770 - 776
  • [6] An on-line fault detection scheme for SBoxes in secure circuits
    Di Natale, G.
    Flottes, M. L.
    Rouzeyre, B.
    13TH IEEE INTERNATIONAL ON-LINE TESTING SYMPOSIUM PROCEEDINGS, 2007, : 57 - 62
  • [7] On-line fault detection technique for voltage transformers
    Lei, Ting
    Faifer, Marco
    Ottoboni, Roberto
    Toscani, Sergio
    MEASUREMENT, 2017, 108 : 193 - 200
  • [8] Adaptive BIST for Concurrent On-Line Testing on Combinational Circuits
    Chioktour, Vasileios
    Kakarountas, Athanasios
    ELECTRONICS, 2022, 11 (19)
  • [9] Optimal seed generation for delay fault detection BIST
    Tong, LH
    Suzuki, K
    Ito, H
    PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS 02), 2002, : 116 - 121
  • [10] Optimal seed generation for delay fault detection BIST
    Graduate Sch. of Sci. and Technol., Chiba Univ., Japan
    不详
    Proc Asian Test Symp, 1600, (116-121):
12345