An on-line BIST technique for delay fault detection in CMOS circuits

被引：0
|
作者：
Moghaddam, Elham K. [1 ]
Hessabi, Shaahin [1 ]
机构：
[1] Sharif Univ Technol, Dept Comp Engn, Tehran, Iran
来源：
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM | 2007年
关键词：
delay fault; online testing; BIST techniques; robust delay test; design for testability;
D O I：
10.1109/ATS.2007.100
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a simulation-based study of the delay fault testing in CMOS logic circuits. A novel built-in self-test (BIST) technique is presented for detecting delay faults in this logic family. This scheme does not need test-pattern generation, and thus can be used for robust on-line testing. Simulation results for area, delay, and power overheads are presented.
引用
收藏
页码：73 / 76
页数：4
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