Formal specification and verification of VHDL

被引：0
|
作者：
Bickford, M [1 ]
Jamsek, D [1 ]
机构：
[1] Odyssey Res Associates, Ithaca, NY 14850 USA
来源：
FORMAL METHODS IN COMPUTER-AIDED DESIGN | 1996年 / 1166卷
关键词：
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
We give an overview of our system for the verification of VHDL designs(1), and discuss its rationale. We present a complete example of a simple processor and discuss general methods for specification of state machines and timed and untimed combinational circuits.
引用
收藏
页码：310 / 326
页数：17
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