Semi-formal verification of VHDL-AMS descriptions

In this paper a new technique for functional verification of VHDL-AMS descriptions is proposed The technique is based on combining equivalence checker, analog simulator, and term rewriting engine in a single tightly coupled verification environment. The proposed method verifies the equivalence between two VHDL-AMS architectures describing alternative implementation or different abstraction level for the same AM/S design entity. The verification process is based on building comparator circuits for the analog outputs and miter circuits for the digital outputs. The miter circuit is verified using novel SAT/BDD equivalence checking algorithm. The analog comparator circuit is verified using set of rewriting rules. The equivalence of D/A & A/D converters is proved using matching procedure.