Feasibility of using W/TiN as metal gate for conventional 0.13μm CMOS technology and beyond

We demonstrate the feasibility of using W/TiN as metal-gate on thin gate dielectrics (less than or equal to 33 Angstrom and with high temperature (>950 degrees C) S/D annealing for 0.13 mu m CMOS applications. Close to ideal C-V characteristics are obtained indicating good Si/SiO2 interface quality and free from gate depletion. The gate sheet resistance is about 2ohm/square, nearly constant down to 0.05 mu m. Under fixed effective fields, the electron and hole mobility are comparable to or slightly better than those of poly gate devices. Compared to poly gate devices, the W/TiN on 33 Angstrom pure oxide has inferior charge-to-breakdown (Cbd) distribution under substrate (+V-G) injection. However, a remote-plasma nitrided oxide (RPNO) [1] can greatly improve the +V-G Q(bd) distribution for the W/TiN case. Short-channel W/TiN pMOS transistors are fabricated with excellent characteristics down to L(gate)approximate to 0.07 mu m. For nMOS under +V-G direct-tunneling (DT) or Fowler-Nordheim (F-N) tunneling injection with S/D grounded, the W/TiN device has a higher substrate hole current density (J(p)) than n(+) poly-gate device (by about an order magnitude larger). This higher J(p) is believed due to the tunneling of valance-band electron and thus has no impact on the thin (t(ox)less than or equal to 33 Angstrom) gate oxide reliability.