0.13μm CMOS technology with optimized poly-Si/NO-oxide gate stack.

被引：0

作者：

Kubicek, S ^{[1
]}

Jansen, P ^{[1
]}

Badenes, G ^{[1
]}

Schaekers, M ^{[1
]}

Koldyaev, V ^{[1
]}

Deferm, L ^{[1
]}

De Meyer, K ^{[1
]}

机构：

[1] IMEC, B-3001 Heverlee, Belgium

来源：

ULSI PROCESS INTEGRATION | 1999年 / 99卷 / 18期

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 0.13 mu m CMOS technology with an optimized poly-Si / NO-oxide gate stack is presented. Trade-off's between NO-oxide and pure SiO2 and between B and BF2 as HDD dopants are analyzed. The effect of various NO-oxides on nMOS and pMOS transistor characteristics is clearly demonstrated and explained. It is shown that careful optimization of the channel, S/D extensions and HALO's provides efficient SCE (short channel effect) suppression down to 0.13 mu m poly lengths (as measured by SEM after the dry poly etch). Flat V-T=f(L-poly) characteristics with drive currents of 630 mu A/mu m and 330 mu A/mu m (off state currents less than 1nA/mu m) measured at V-DD=1.5V for nMOS and pMOS respectively are achieved.

引用

页码：193 / 202

页数：10

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