0.13μm CMOS technology with optimized poly-Si/NO-oxide gate stack.

A 0.13 mu m CMOS technology with an optimized poly-Si / NO-oxide gate stack is presented. Trade-off's between NO-oxide and pure SiO2 and between B and BF2 as HDD dopants are analyzed. The effect of various NO-oxides on nMOS and pMOS transistor characteristics is clearly demonstrated and explained. It is shown that careful optimization of the channel, S/D extensions and HALO's provides efficient SCE (short channel effect) suppression down to 0.13 mu m poly lengths (as measured by SEM after the dry poly etch). Flat V-T=f(L-poly) characteristics with drive currents of 630 mu A/mu m and 330 mu A/mu m (off state currents less than 1nA/mu m) measured at V-DD=1.5V for nMOS and pMOS respectively are achieved.