A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

被引：0
|
作者：
Ishii, K [1 ]
Kishine, K [1 ]
Ichino, H [1 ]
机构：
[1] NTT, Network Innovat Labs, Yokosuka, Kanagawa 2390847, Japan
来源：
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique improves both the jitter generation and the jitter transfer function. The jitter generation can be suppressed by boosting the loop gain in PLL. A suitable jitter transfer function and jitter tolerance can be achieved by optimizing the characteristics of a surface acoustic wave (SAW) filter. The fabricated circuit had a low jitter generation (about 2.4 mUI rms) and a low jitter transfer function cutoff frequency (about 500 kHz) by using a SAW filter with a center frequency (f(c)) of 622.08 MHz. The jitter generations are within 5 mUI rms for the temperature range between 0 degrees C to 90 degrees C. The circuit passes the jitter tolerance specification in ITU-T recommendation G.958 by more than 30%.
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页码：261 / 264
页数：4
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