Low Power Design for Source Coupled Logic Gates

This paper presents a new technique for lowering power dissipation of Source Coupled Logic (SCL) circuits. Variants of SCL such as MOS Current Mode Logic (MCML) and Positive Feedback Source Coupled Logic (PFSCL) suffer from the disadvantage that implementing complex logic function requires stacking of transistor and/or cascading of gates which negatively affects the minimum power supply required and the delay respectively. With MCML and PFSCL triple tail based implementation, while the previous issues are solved the issue of constant bias current still remains. Here, a generic technique to lower the minimum required power supply voltage is presented which is applied to the constant current source transistor in current mode logic, which in turn reduces the minimum power supply required. To verify the behavior, two input XOR gate based on proposed technique has been implemented in MOS current mode logic based triple tail and PFSCL based Triple Tail and has been simulated. The use of proposed technique shows improvement in power dissipation of 18% for 100uA bias current, proportional to the reduction in the minimum power supply voltage. Simulations have been carried out in ORCAD PSPICE using TSMC CMOS 180nm technology. To verify the behavior of the proposed technique under process variations, process corner analysis has been carried out and the circuit shows maximum variation of 12.5% in the voltage swing. The proposed technique does not negatively impact the delay.