Programmable low-frequency divider in 180-nm CMOS technology

被引：0

作者：

Tomic, Dubravko ^{[1
]}

Mikulic, Josip ^{[2
]}

Schatzberger, Gregor ^{[2
]}

Fellner, Johannes ^{[2
]}

Baric, Adrijan ^{[1
]}

机构：

[1] Unitvers Zagreb, Fac Elect Engn & Comp, Unska 3, Zagreb 10000, Croatia

[2] amsAG, Tobelbader Str 30, A-8141 Premstatten, Austria

来源：

2020 43RD INTERNATIONAL CONVENTION ON INFORMATION, COMMUNICATION AND ELECTRONIC TECHNOLOGY (MIPRO 2020) | 2020年

关键词：

frequency divider; 180-nm CMOS technology; microelectronics; chip-design;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design and measurements of a programmable frequency divider that converts the input clock of 32 kHz to 1 Hz. The circuit is designed, simulated and the layout is drawn in Cadence simulation environment. The binary counter used in the circuit design is synchronous counter with asynchronous reset. The output frequency drift is measured and compared with simulation results for the varying supply voltage from 1.1 to 1.3 V and temperature from -40 degrees C to 80 degrees C.

引用

页码：89 / 92

页数：4

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