A Novel 8.4 GHz, High Speed and Low Power Design of Programmable Divider in 180nm CMOS Technology

被引：0
|
作者：
Purohit, Smita [1 ]
Nirmal, Uma [1 ]
机构：
[1] Mody Univ, Lakshmangarh, Rajasthan, India
来源：
2019 2ND INTERNATIONAL CONFERENCE ON INTELLIGENT COMMUNICATION AND COMPUTATIONAL TECHNIQUES (ICCT) | 2019年
关键词：
Multi-modulus prescaler; divided by by-2 vertical bar 3 prescaler; Transmission gate; True -single phase clock (TSPC); multiplexer (MUX);
D O I：
10.1109/icct46177.2019.8968776
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
In this paper, a power efficient and fast divide - (divided by) - by 32 vertical bar 33 vertical bar 47 vertical bar 48 multi - modulus prescaler having operating frequency of 8.4 GHz is proposed using a 0.18 mu m CMOS technology. The proposed design includes a wideband high operating speed and low power divided by - by 2 vertical bar 3 prescaler, improvised divided by - by 2 counters, transmission gate-based MUX and logical gates to switch between division ratios 32 vertical bar 33 vertical bar 47 vertical bar 48. The power consumption of novel design is 0.2368 mu W, 0.2287 mu W, 0.2844 mu W and 0.2785 mu W during division ratio of 32, 33, 47 and 48, respectively when worked at 0.6 V of power supply. The operating speed of design is improved by 14.2% as compared with the conventional design.
引用
收藏
页码：192 / 195
页数：4
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