Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

被引：32

作者：

Ko, Cheng-Ta ^{[1
]}

Yang, Henry ^{[1
]}

Lau, John H. ^{[2
]}

Li, Ming ^{[3
]}

Li, Margie ^{[2
]}

Lin, Curry ^{[1
]}

Lin, J. W. ^{[1
]}

Chen, Tony ^{[4
]}

Xu, Iris ^{[4
]}

Chang, Chieh-Lin ^{[5
]}

Pan, Jhih-Yuan ^{[5
]}

Wu, Hsing-Hui ^{[5
]}

Yong, Qing Xiang ^{[7
]}

Fan, Nelson ^{[2
]}

Kuah, Eric ^{[2
]}

Li, Zhang ^{[4
]}

Tan, Kim Hwee ^{[4
]}

Cheung, Yiu-Ming ^{[2
]}

Ng, Eric ^{[2
]}

Kai, Wu ^{[2
]}

Hao, Ji ^{[2
]}

Beica, Rozalia ^{[5
]}

Lin, Marc ^{[6
]}

Chen, Yu-Hua ^{[1
]}

Cheng, Zhong ^{[7
]}

Wee, Koh Sau ^{[7
]}

Ran, Jiang ^{[7
]}

Xi, Cao ^{[7
]}

Lim, Sze Pei ^{[8
]}

Lee, N. C. ^{[8
]}

Tao, Mian ^{[9
]}

Lo, Jeffery ^{[9
]}

Lee, Ricky S. W. ^{[9
]}

机构：

[1] Unimicron Technol Corp, Hsinchu 304, Taiwan

[2] ASM Pacific Technol Ltd, Hong Kong, Hong Kong, Peoples R China

[3] ASM Pacific Technol Ltd, Enabling Technol, Hong Kong, Hong Kong, Peoples R China

[4] Jiangyin Changdian Adv Packaging Corp Ltd, Jiangyin 214431, Peoples R China

[5] Dow Chem Co USA, Marlborough, MA 01752 USA

[6] Dow Chem Co USA, PCB Business, Marlborough, MA 01752 USA

[7] Huawei Technol Corp Ltd, Shenzhen 51800, Peoples R China

[8] Indium Corp, Utica, NY 13502 USA

[9] Hong Kong Univ Sci & Technol, Dept Mech Engn, Hong Kong, Hong Kong, Peoples R China

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2018年 / 8卷 / 09期

关键词：

Fan-out panel-level packaging (FOPLP); heterogeneous integration; redistribution layer; WARPAGE;

D O I：

10.1109/TCPMT.2018.2848665

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips by a fanout panel-level packaging (FOPLP) method are investigated in this paper. Emphasis is placed on the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. The electroless Cu is used to make the seed layer, the laser direct imaging is used for opening the photoresist, and the printed circuit board Cu plating is used for making the conductor wiring of the RDLs. Reliability assessments such as the drop test and thermal cycling test are also performed.

引用

页码：1561 / 1572

页数：12

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