FPGA-based digit-serial complex number multiplier-accumulator

被引：0

作者：

Sansaloni, T ^{[1
]}

Valls, J ^{[1
]}

Parhi, KK ^{[1
]}

机构：

[1] Univ Politecn Valencia, Dpto Ing Elect, EPS Gandia, Grao De Gandia 46730, Spain

来源：

ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a FPGA implementation of digit-serial Complex Number Multiplier-Accumulators (CMACs) based on Booth recoding techniques and Carry Save (CS) adders. The Complex Number Multiplier-Accumulators can be pipelined at LUT-level. An efficient mapping of the Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5-3 and 4-3 converter in the CS structure and the utilization of Ripple Carry Adder (RCA) trees lead to a minimum area requirement.

引用

页码：585 / 588

页数：4

共 50 条

[31] A digit-serial multiplier for finite field GF(2m)
Kim, CH
Hong, CP
Kwon, S
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (04) : 476 - 483
[32] Area/performance trade-off analysis of an FPGA digit-serial GF(2m) Montgomery multiplier based on LFSR
Morales-Sandoval, M.
Feregrino-Uribe, C.
Kitsos, P.
Cumplido, R.
COMPUTERS & ELECTRICAL ENGINEERING, 2013, 39 (02) : 542 - 549
[33] Digit-Serial GNB Multiplier Based on TMVP Approach over GF(2m)
Yang, Chun-Sheng
Pan, Jeng-Shyang
Lee, Chiou-Yng
2013 SECOND INTERNATIONAL CONFERENCE ON ROBOT, VISION AND SIGNAL PROCESSING (RVSP), 2013, : 123 - 128
[34] Digit-serial systolic multiplier for finite fields GF(2m)
Guo, JH
Wang, CL
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, 1998, 145 (02): : 143 - 148
[35] Super Digit-Serial Systolic Multiplier Over GF(2m)
Lee, Chiou-Yng
2012 SIXTH INTERNATIONAL CONFERENCE ON GENETIC AND EVOLUTIONARY COMPUTING (ICGEC), 2012, : 509 - 513
[36] Low-latency digit-serial dual basis multiplier for lightweight cryptosystems
Chiou, Che Wun
Lee, Chiou-Yng
Lin, Jim-Min
Yeh, Yun-Chi
Pan, Jeng-Shyang
IET INFORMATION SECURITY, 2017, 11 (06) : 301 - 311
[37] Digit-serial multiplier design using skew-tolerant domino circuits
Kim, S
Sobelman, GE
14TH ANNUAL IEEE INTERNATIONAL ASIC/SOC CONFERENCE, PROCEEDINGS, 2001, : 356 - 360
[38] Design of adiabatic two's complement multiplier-accumulator based on CTGAL
Wang, Peng-jun
Xu, Jian
Ying, Shi-yan
JOURNAL OF ZHEJIANG UNIVERSITY-SCIENCE A, 2009, 10 (02): : 172 - 178
[39] Design of adiabatic two’s complement multiplier-accumulator based on CTGAL
Peng-jun Wang
Jian Xu
Shi-yan Ying
Journal of Zhejiang University-SCIENCE A, 2009, 10 : 172 - 178
[40] Design of adiabatic two's complement multiplier-accumulator based on CTGAL
Peng-jun WANG1
Journal of Zhejiang University-Science A(Applied Physics & Engineering), 2009, 10 (02) : 172 - 178

← 1 2 3 4 5 →