FPGA-based digit-serial complex number multiplier-accumulator

被引：0
|
作者：
Sansaloni, T [1 ]
Valls, J [1 ]
Parhi, KK [1 ]
机构：
[1] Univ Politecn Valencia, Dpto Ing Elect, EPS Gandia, Grao De Gandia 46730, Spain
来源：
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a FPGA implementation of digit-serial Complex Number Multiplier-Accumulators (CMACs) based on Booth recoding techniques and Carry Save (CS) adders. The Complex Number Multiplier-Accumulators can be pipelined at LUT-level. An efficient mapping of the Booth recoding and the partial product generation is presented which results in a logic depth reduction. The combination of 5-3 and 4-3 converter in the CS structure and the utilization of Ripple Carry Adder (RCA) trees lead to a minimum area requirement.
引用
收藏
页码：585 / 588
页数：4
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