Characterization of a Novel 10T Low-Voltage SRAM Cell With High Read and Write Margin for 20nm FinFET Technology

In this paper, a new ten transistors (10T) SRAM bit-cell with differential read and write operations is proposed. The proposed bit-cell has six main body transistors similar to 6T bit-cell to perform write operation along with separate bitline discharging path (2T) on each side to perform read operation. Efficacy of the proposed bit-cell is tested in 20nm tri-gated FinFET technology with the help of HSPICE simulations at different supply voltages (0.6V to 0.9V). Performance characteristics of the proposed bit-cell are compared with the recently reported 10T P-P-N bit-cell as well as the commercial 6T cell. The proposed bit-cell achieves 12% and 41% higher RSNM as compared to that of 10T P-P-N and 6T bit-cells respectively at VDD of 0.6V. WM of proposed bit cell is 34.88% higher and comparable to that of 10T P-P-N and 6T bit-cell respectively at VDD of 0.6V. Influence of process variation on proposed bit-cell stability is studied using 5,000 Monte Carlo simulations. The study shows that proposed bit cell meets the required cell sigma value (643) for all operations at VDD of 0.6 V.